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Obtaining Optimum Performance with Summit's ADOC™/Marginer Family

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INTRODUCTION

Systems are migrating from distributed power architectures to Point-of-Load (POL) design to gain better regulation and control at the load. Providing power at the load gives superior regulation transient response and avoids voltage drops across PCB traces and planes. This is necessary as voltage levels decrease and allowable supply variations around these levels also decrease. These tighter voltage limits demand accurate control especially under full load conditions to maintain performance.

  
Summit's family of Active DC Output Controllers (ADOC™) was designed to accurately control the voltage accuracy and margining of DC-DC converters. The SMM105 is targeted for POL (Point Of Load) applications requiring extremely accurate control of the converter's voltage while the SMM205/605/665 for centralized applications where multiple voltages are used. The information in this App Note is intended to focus on obtaining the highest possible performance from Summit's Marginers and to avoid creating unnecessary problems by presenting a more detailed functional description of these devices.
 
Why Margin?

Voltage margining is performed in systems to test components at their worst case operating voltage extremes in order to find weak or marginal devices and replace them to improve overall reliability. For example, a 3.3V supply may be margined to a logic family's high operating voltage of 3.465V (+5%) and to its low operating voltage of 3.135V (-5%). Summit's marginers provide an additional measure of safety to voltage margining by accurately setting the target supply to its nominal voltage prior to margining. This practice greatly enhances the usefulness of voltage margining by improving the inherent ±2% to ±4% nominal stated accuracy of the DC-DC converter to ±0.2% to ensure the target margin voltage does not under or over-stress the components in question when the margin voltage is added (or subtracted) with an inaccurate nominal supply voltage.

Make certain that when choosing an existing marginer solution, the overall accuracy is well understand and is not hidden in some obscure specification not readily found in the manufacturer's data sheet. For example, one vendor advertises a margin accuracy of <0.4% but upon further examination of the vendor's data sheet and after performing numerous calculations it is found the advertised accuracy is only attainable when the vendor's device and the external components contain no inaccuracies. Summit's marginers require little or no calculations due too the active feedback adjustment of the output level. The only sources of margin inaccuracies are the marginer itself and the external reference, if used. Summit's advertised accuracy is easily attained without component tuning or selection.

Accuracy

Of the marginer family, the SMM665 contains two functional blocks both of which are designed for high accuracy. The ADOC block is that portion of the device that controls the DC-DC converter output voltage and the ADC block is the portion that monitors the converter voltages and is also available to the user as digital data.

Obtaining ADOC Accuracy The base accuracy of the marginer ADOC function is ±0.1% over temperature plus the accuracy of the reference used. To obtain ±0.2% accuracy an inexpensive ±0.1% external reference is commonly used. When the internal reference is used the ADOC accuracy is ±0.5% across temperature. To ensure this accuracy is achieved, locate the external voltage reference near the marginer; making a direct PCB trace connection from the low side of the voltage reference to the marginer's GND pin (Fig. 1) and from the reference output pin to the marginer VREF_CNTL pin (Fig. 1).
		Figure 1. VREF to SMM665 PCB Connection

Although it may be convenient to make the GND connections to an inner layer using a copper via, the method shown in Figure 1 is preferred because it is unaffected by other currents returning to the GND pin. Make certain to use a bypass capacitor (C1) from the reference output to GND as recommended by the manufacturer. If using the marginer's internal reference bypass the VREF_CNTL pin directly to the GND pin with a 0.1µF ceramic capacitor.