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Lossless Tracking Procedure and Results Summary Reference Design: Volterra VT223 Regulator and SMT4214 TRAKKER

PAGE 5

Powering The Xilinx Vertex E FPGA

To power the Xilinx Vertex E FPGA is the VT223 Evaluation Board is modified to:

	1.	Increase the output voltage from 1.5V to 1.8V.
	2.	Desensitize the VT223 from track down anomalies.

To increase the output voltage first determine the new value of RREF:

The following changes to the VT223 Evaluation Board circuit were made to prevent the STAT output from being effected by the track-down event:

	1.	Increase the value of R9 from 10k to 25k.
	2.	Change C8 from 0.01uF to 1000pF.
	3.	Replace R7 (100k) with a zero ohm jumper.

Finally, the SMT4214 program settings are modified to allow the core voltage (VCCINT, 1.8V) to turn on before the I/O supply (VCCO, 3.3V). A simplified schematic of the circuit is displayed in Figure 9. The complete schematic is shown in Figure 14.

 
Performance Results

The resulting track-up waveforms into the Xilinx FPGA are displayed in Figures 10 and 11. Note the 1.8V ramps on first followed by the 3.3V.

The value of C_G and the gate voltage VGATEV level directly affects the rise time of the 1.8V supply voltage as well as the delay between the 1.8V and 3.3V supplies.

The waveform in Figure 10 uses a 2uF value for the CG capacitor and a VGATEV voltage of 10.5V while Figure 11 uses a 2uF capacitor with 14.5V and Figure 12/13 uses 3uF with 10.5/14.5V VGATEV.

Note:The slight voltage 'lift' occurring on the 3.3V output (channel 1, yellow) is of no consequence but if deemed necessary can be reduced by adding a suitable resistive load from the 3.3V output node to ground. Start with a 1k½.