Summit Microelectronics - Applications Note 29

Tech Support: Applications Note 29
SMH4804 -48V Programmable Hot Swap Sequencing Power Controller Windows GUI Users Guide and Configuration Register Descriptions

Application Note 29

1 2 3 4 5 6 7 8 9

10 11 12 13 14 15 16 17 18

SPECIAL NOTE: The HTML version of the application note has been divided into multiple pages to follow the PDF version. You may use the menu here to jump to any of the other pages. You may also download/view the entire application note in PDF format [PDF format].

SMH4804 - Windows GUI Users Guide and Configuration Register Descriptions

PAGE 8

Register R05 - Latch function, FS# pin function, Cascade mode.
Register 5 controls the function of the nonvolatile fault latch and provides general control for the FS# input. Bit 3 controls the enabling of the non-volatile latch. Bits 2:0 configure the FS# input. The FS# pin has two basic functions: it can be programmed to act as an auxiliary enable input controlling the PG1# output, or it can be programmed to be an event monitor during the power-up sequence. These bits also control the interrelationship of the PG[4:1]# outputs. In a cascade operating mode PG1# must be true before PG2# can be true, etc. This interrelationship can be disabled so that each PG[4:1]# output is effectively controlled by its corresponding ENGPx# input, as long as the primary supply, VGATE and DRAIN SENSE pins are within their operating limits.

When programmed as an enable to PG1# there are two options: 010BIN disables the cascade mode (the PG[4:1]# outputs can act independently) and FS# effectively becomes the enable input for PG1#; 011BIN enables the cascade mode and makes FS# the enable input for PG1#. In this mode, PG1# must be active before PG2# can be activated, followed by PG3#, then PG4#.

The event monitor mode is generally implemented in conjunction with a monitoring device on the secondary side of the DC/DC converters, such as the SMS44, SMT4004 or SMS64. If FS# is not pulled high before the programmed condition then the PG[4:1]# and VGATE outputs are shut down. As an example, if the binary value is 111BIN, VGATE and PG1# are shut down if FS# is not pulled high before tPGD has elapsed after PG1# is true. None of the other PG[4:1]# outputs are activated. If a failure occurs due to the lapse of the event monitor timer, cycling the power resets the device.

One last event mode, 000BIN, disables the cascade effect and sets up PG4# going true as the trigger event. FS# must be pulled high before tPGD elapses, or VGATE and all of the PG[4:1]# outputs are disabled. Cascade enabled:

ENPGA enables PG2#, PG3# and PG4#;

ENPGB enables PG3# and PG4#;

ENPGC enables PG4#.

Cascade disabled:

ENPGA enables PG2#;

ENPGB enables PG3#;

ENPGC enables PG4#.

Simultaneous:

PG1#, PG2#, PG3# and PG4# operate independently from one another.

Sequenced:

PG1#, PG2#, PG3# and PG4# are dependent upon activation of PG(N&endash;1) - for N = 2, 3, and 4 - plus a programmable PG delay.p=On

NOTICE

SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user's specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission.

SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances.

Revision 1.0 - This document supersedes all previous versions and covers Windows GUI revision 2.3.0 and later. Please check the Summit Microelectronics, Inc. web site at www.summitmicro.com for updates.