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Designing
a NEBS-compliant Power System -
SMH4804
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Pre-Testing
for NEBS Compliance,
Cont'd
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The
scope photo in Figure 8 shows the effect of the
500V amplitude burst pattern on the &endash;48Volts
supply following the protection circuit. Channel 1
monitors the burst following the protection circuit
and before the first EMI filter. Channel 2 monitors
the burst pattern after the first EMI filter.
Channel 3 monitors the burst pattern after the
Summit Microelectronics' SMH4804 device (see Figure
10) and channel 4 monitors the burst pattern after
the second EMI filter. The varying amplitudes of
the waveforms indicate the degree of attenuation
each section contributes to 'squelching' the burst
waveform disturbance.
As shown, the protection circuitry clamped the
burst voltages to approximately 60 Volts. No
circuitry was damaged using the Level 1(+/-500
Volts) waveform.
The burst voltage is then increased to Level 2,
+/-1000 Volts. The burst pattern was then applied
to the board with no damage occurring. This infers
the DUT is NEBS compliant against the burst
tests.
It is useful to extend the testing to at least 125%
of the required compliance amplitude to be assured
of obtaining NEBS compliance on all production
boards.
The tests were increased to see how far the NEBS
board could be taken before it was damaged. It is
also useful to determine the amplitude at which a
hard failure occurs.
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Figure
8: Results of the 500V Burst Test Pattern
at Various Points on the DUT (see
text)
Tektronix TDS3054
Time/Horizontal division = 100nS
Channel 1-4 = 20V/div, All scope probe
returns connected to U13-3, & 4
Ch 1 = -48V (Yellow trace)
Ch 2 = U13-5, 6 (Blue trace)
Ch 3 = U17-1, 2 (Purple trace)
Ch 4 = U17-5, 6 (Green trace)
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The Level 3 (+/-2000 Volts) test pattern was
applied to the NEBS board with no hard failures. In
fact, this system passed the Level 4 requirements
of +/-4000 Volts. This is the maximum level of
protection this board can offer before a hard
failure occurs.
The next test is the surge test. Figure 9 displays
the Windows setup for the surge voltage
waveform.
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SUMMIT
Microelectronics, Inc. reserves the right
to make changes to the products contained
in this publication in order to improve
design, performance or reliability. SUMMIT
Microelectronics, Inc. assumes no
responsibility for the use of any circuits
described herein, conveys no license under
any patent or other right, and makes no
representation that the circuits are free
of patent infringement. Charts and
schedules contained herein reflect
representative operating parameters, and
may vary depending upon a user's specific
application. While the information in this
publication has been carefully checked,
SUMMIT Microelectronics, Inc. shall not be
liable for any damages arising as a result
of any error or omission.
SUMMIT Microelectronics, Inc. does not
recommend the use of any of its products
in life support or aviation applications
where the failure or malfunction of the
product can reasonably be expected to
cause any failure of either system or to
significantly affect their safety or
effectiveness. Products are not authorized
for use in such applications unless SUMMIT
Microelectronics, Inc. receives written
assurances, to its satisfaction, that: (a)
the risk of injury or damage has been
minimized; (b) the user assumes all such
risks; and (c) potential liability of
SUMMIT Microelectronics, Inc. is
adequately protected under the
circumstances.
Revision 1.1 - This document supersedes
all previous versions and covers Status
Tracking Codes up to 10 and Windows GUI
revision 2.39.3 and later. Please check
the Summit Microelectronics, Inc. web site
at www.summitmicro.com
for data sheet updates.
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Copyright
© 2003 SUMMIT MICROELECTRONICS, Inc.
Power Management for Communications™
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